This invention relates generally to a semiconductor device and method of fabrication, and especially to semiconductor devices which have been fabricated using trench isolation technology to produce narrow and wide element isolation regions.
Typically, a semiconductor device employing a trench isolation method to produce isolation regions, forms trenches by reactive ion etching (RIE) of the substrate of the semiconductor. Depending, in part, upon the width of the trench etched, the trench is classified as either a narrow or wide element isolation region. Once the trench is formed, an insulating film, such as silicon oxide, is applied by, for example, chemical vapor deposition (CVD) to the surface of the substrate as well as within the trenches. The surface of the substrate is then etched such that the insulating film remains only within the trenches. For trenches of approximately four micrometers or more, which are considered wide element isolation regions, the insulating film is frequently of uneven thickness and can be so sparse as to leave large gaps within the trench where no insulating film exists whatsoever. Consequently, an undesirable capacitive effect between the insulating material and substrate, short circuiting or other undesirable effects of circuitry disposed within the trench can occur.
Japanese Laid Open Patent Application Nos. 55-78540, 56-94646 and 56-94647 have attempted to solve some of the above noted drawbacks but are unable to consistently fabricate wide element isolation regions in a submicron semiconductor device. Further, trench isolation technology is disclosed by Mikoshiba, et al. of NEC Corporation in an article from a 1984 IEDM Publication on pages 578-581.
Accordingly, it is desirable to provide an improved semiconductor including narrow and wide isolation regions which overcome the problems associated with the prior art devices.